The present invention relates to a semiconductor memory device including a plurality of programmable read only memory (PROM) cells arranged in a matrix of rows and columns, and it particularly relates to two column transfer gate transistor groups independently provided for a sense amplifier and a programming circuit of the memory device.
FIG. 1 is a schematic diagram of the prior art memory device showing a part related to the present invention. In FIG. 1, a reference symbol QM shows a plurality of PROM cells arranged at intersection points of a matrix formed by a plurality of word-lines WL.sub.0 through WL.sub.m and bit-lines BL.sub.0 through BL.sub.n crossed each other. When an address signal A comes into both of a column decoder 1 and a row decoder 2, the decoders 1 and 2 produce column selecting signals Y.sub.0 through Y.sub.n and row selecting signals X.sub.0 through X.sub.m respectively. Column transfer gate transistors T.sub.0, T.sub.1, and T.sub.n are connected to bit-lines BL.sub.0, BL.sub.1, and BL.sub.n respectively, and each column transfer gate transistor consists of a field effect transistor having a source connected to both of a sense amplifier 3 and a programming circuit 4, a drain connected to the bit-line BL.sub.0, BL.sub.1, or BL.sub.n, and a gate connected to the column decoder 1 to receive the column selecting signal Y.sub.0, Y.sub.1, or Y.sub.n When the address signal A is applied to the memory device, one of the row selecting signals X.sub.0 through X.sub.m is applied to one of the word-lines W.sub.L through WL.sub.m, and one of the column selecting signals Y.sub.0 through Y.sub.n is applied to a gate of one of the column transfer gate transistors T.sub.0 through T.sub.n.
When the memory device is in a state of programming a data signal given from the exterior of the memory device, the state will be called as "a programming mode" hereinafter, a PROM cell must be selected from the PROM cells arranged in the matrix, by both of a row selecting signal (X.sub.0, X.sub.1, or X.sub.m) and a column selecting signal (Y.sub.0, Y.sub.1, or Y.sub.n), and the programming circuit 4 is connected to the selected PROM cell by a selected column transfer gate transistor (T.sub.0, T.sub.1, or T.sub.n so that the data signal applied from the exterior of the memory device is transferred and programmed into the selected PROM cell.
When the memory device is in a state of reading a data signal stored in a selected PROM cell, the state will be called as "a reading mode" hereinafter, the PROM cell is selected the same of the above, and the sensing amplifier is connected to the selected PROM cell by a selected column transfer gate transistor (T.sub.0, T.sub.1, or T.sub.n) so that the data signal stored in the selected PROM cell is read out and transferred to the sense amplifier 3 and amplified.
In FIG. 1, the source of every transfer gate transistor is connected to both of the sense amplifier 3 and the programming circuit 4. However, functionally, either of the sense amplifier 3 or the programming circuit 4 is selected by switching circuits, which are not depicted in FIG. 1, located in the sense amplifier 3 and the programming circuit 4 respectively and controlled by a read-write selecting signal 6 applied from the exterior of the memory device.
FIG. 2 is a schematic diagram of the prior art showing the relation between the column decoder 1 and the selected column transfer gate transistor T.sub.i (i indicates one of the numerals 0 through n). In FIG. 2, the same reference numeral or symbol as in FIG. 1 designates the same unit or part as in FIG. 1, and a metal oxide semiconductor (MOS) transistor is used for all transistors; wherein, a transistor having no mark is an n-channel enhancement type transistor, a transistor having a black dot is an n-channel depletion type transistor, and a transistor having an arrow mark is a p-channel type transistor. When the address signal A consisting of binary signals a.sub.i, a.sub.j, and a.sub.k are applied to a NAND gate 101 of the column decoder 1 so that the binary signals are all in a high (H) level, the output level of the NAND gate 101 becomes low (L), and a buffer inverter 102 of the column decoder 1 produces a column selecting signal Y.sub.i having an H level, so that a column transfer gate transistor T.sub.i becomes conductive. As a result, when the memory device is in the reading mode, the sensing amplifier 3 is connected to the selected PROM cell on a bit-line BL.sub.i, and when the memory device is in the programming mode, the programming circuit 4 is connected to the selected PROM cell. A power supply voltage V.sub.ppi for the NAND gate 101 and the buffer inverter 102 is variable. When the memory device is in the programming mode, the power supply voltage V.sub.ppi becomes a high voltage (for example 21 volts (V)) so that the bit-line is held high with a high voltage (for example 15 V) for programming the data signal into the selected PROM cell. When the memory device is in the reading mode, the voltage V.sub.ppi is switched to a low voltage (for example 5 V).
Recently, a memory device is required to have a fast access time, particularly in the reading mode. However, in the prior art, there is a problem that the memory device cannot operate at high speed in the reading mode because the column transfer gate transistor is commonly used for programming and reading out the data signal. In FIG. 2, a large current is required to flow through the transistor T.sub.i, in the programming mode, for programming the data signal into the selected PROM cell on the bit-line BL.sub.i. Therefore, a channel width of the transistor T.sub.i must be large, which causes an increase in p-n junction capacitance formed between a substrate and a source or drain region of the transistor T.sub.i. This large stray capacitance becomes a heavy load for the sensing amplifier 3 and the PROM cell, so that a data sensing speed obtained in the sense amplifier 3 becomes slow. Furthermore, large capacitance formed between the gate of T.sub.1, T.sub.2, or T.sub.n and its channel also becomes a heavy load for the column decoder 1, so that a rise-time and a fall-time of the column selecting signal (Y.sub.i) are lengthened, which also slow the data access time. A memory device having the PROM cells is usually used in the reading mode, and it is not necessary for the speed of programming the data signal into the selected PROM cell to be high. Thus, the problem stated above is how to realize the fast access time in the reading mode. Increasing the sensitivity of the sense amplifier 3 could be considered for increasing the data reading speed; however, if the sensitivity increases, another problem occurs in that an error due to the noise occurs because the sense amplifier 3 becomes much too critical; such kind of the error cannot be allowed to occur in the memory device. Thus, in the art of designing and fabricating the memory device, a fast access time in the reading mode has been anxiously awaited.